1. Field of the Invention
This invention relates to a speed-matching buffer used to transfer digital signals between two units having different transfer rates; and, more particularly, to a serial speed-matching buffer capable of transferring signals from any one of a plurality of transferring units to one or more receiving units wherein certain ones of the transferring units have different transfer rates from each other and from the receiving units, the transfer being completed with a minimal associated delay and using a minimal number of logic gates.
2. Description of the Prior Art
In complex data processing systems, multiple units having different clock speeds from one another must communicate across interfaces of varying widths, that is, having different numbers of binary digits (bits) transferred in parallel. As a result, a particular receiving unit may receiving data signals from a variety of different transferring units at a number of different transfer rates, none of which matches the rate at which the receiving unit is capable of receiving the data. To remedy this problem, speed-matching buffers are often utilized.
A speed-matching buffer is a storage device that provides an interface between transferring and receiving units that have different transferring and receiving rates, respectively. To avoid an overrun situation, the buffer must be large enough to receive data signals from the unit having the highest transfer rate; and, in turn, provide those data signals to the unit having the lowest receiving rate.
Some prior art speed-matching buffers have been implemented using dual-ported random access memory devices (RAMs). A first unit stores data signals into one or more RAMs at predetermined memory locations, and a second receiving unit later reads the data signals from the same predetermined locations in the RAMs. Although this implementation provides a relatively large amount of buffer space, it is not very fast. Transferring and receiving units can not access the RAMs simultaneously, which slows down throughput. In addition, RAMs that are external to other interfacing logic that is implemented within an application-specific integrated circuit (ASIC) have relatively long "off-chip" access times. Alternatively, memory devices embedded within an ASIC design are faster, but consume a large amount of circuits and silicon area to implement. Finally, dual-ported memories require relatively complex control logic circuits to implement, Instead of using RAMs, many logic designers calculate the worst-case buffer size, then implement the buffer using state devices such as registers. Generally such state devices will have multiple ranks of registers, wherein each rank of registers receives data approximately simultaneously from another rank of registers. Each rank is usually capable of receiving data signals from the unit having the widest interface. On each active portion of the clock signal associated with the transferring unit, data signals are captured from the transferring unit into a first rank of registers, any previously received data signals from the first rank of registers are transferred to a second rank of registers, and so on. The buffer must contain enough ranks of registers to buffer data signals during a transfer between the unit having the highest transfer rate and the unit having the lowest transfer rate or a data overrun could result. Overrun causes loss of data and is unacceptable in most operations.
A speed-matching buffer implemented using ranks of registers is generally faster than RAM-based designs, both because the sending and receiving units may access the buffer simultaneously, and because state devices such as registers generally have faster access times than RAMs. On the other hand, buffers implemented using ranks of registers often produce unwanted delays between the sender and receiver because the first word or words of the transfer may have to be clocked through multiple ranks of the buffer before they can be received by the receiving unit. In addition, as mentioned above, the buffer must contain enough ranks of registers to handle the worst-case scenario, and all ranks of registers are generally designed to receive data from the unit having the widest interface. As a result, many registers in the buffer are not needed during many transfers, and circuits and silicon area are unnecessarily wasted. Finally, the control logic associated with this rank-of-registers design can be relatively complex because control logic sequences are needed to gate the data from the last rank of registers to the receiving unit in increments that match the width of the receiving unit's data path. The control logic sequences will vary based on the width of the transferring unit's data path.